TSMC and Samsung, the two biggest founders on the planet, are already working on the next generations of chips for iPhone and Android smartphones. With the passage to 3 nm and ultimately to 2 nm. Enough to further significantly reduce the component’s energy consumption while making it even more powerful.
For the first time the general public can buy iPhone 12 with a chip engraved in 5 nm. The fineness of engraving is essential in the mobile industry, because it allows put significantly more transistors in a reduced space while significantly reducing energy consumption. However, Apple like many brands does not have its own foundry.
And therefore appealed to industry leaders, including TSMC for quite a few generations now. The new A14 Bionic chip thus embeds 11.8 billion transistors against the 8.5 billion of the A13 Bionic chip of the iPhone 11. Of course we can object that Apple is not alone on the 5 nm: Huawei has just unveiled its new Mate 40 and Mate 40 Pro, with a new Kirin chip 9000 also engraved in 5 nm and which has even more transistors. But in Huawei’s case, the situation is complicated by US sanctions.
Only a handful of founders have access to the essential equipment to burn chips in 5 nm and beyond.
TSMC and competing founders can indeed no longer supply the manufacturer with components since new US sanctions came into force. These sanctions prohibit companies that use American intellectual property from supplying Huawei with components without obtaining the prior approval of the Department of Commerce. Authorization that TSMC did not obtain for Huawei. As a result, of the 15 million Kirin 9000 chips ordered by the Chinese manufacturer, only 8 million have actually been delivered.
This should severely limit Huawei’s sales in the short and medium term. Especially since Huawei did not intend to use the Kirin 9000 only on the Mate 40 – but also in its 5G network solutions and its foldable smartphone Mate X2. Only one other actor is thus supposed to join the 5nm club from next year: Samsung with its next Exynos chip and the Snapdragon 875 that it should burn for Qualcomm. Gold, Samsung and TSMC are already working with Dutch OEM ASML on 3nm and 2nm engraving.
The opportunity to immerse yourself in the increase in engraving finesse, as well as in the central role of OEMs like ASML to deliver ever more efficient chips. By the way, Huawei has been looking since the start of the trade war for alternatives to avoid seeing its supply of high-performance chips disappear. China does have a national founder, SMIC, but its engraving processes are still lagging behind the competition (14 nm and soon 7 nm).
Innovations multiply as fundamental limits are reached
This is the case precisely because equipment manufacturers like ASML no longer have the right to supply these players with the latest machines. The more the engraving fineness is reduced, the more we push back the limits of what is technically possible to do, especially as strange effects appear. It is therefore necessary to adopt ever more sophisticated tricks to maintain constant engraving precision, and to avoid the effects of current leaks, or of disturbances which take the upper hand after a certain threshold.. For 5 nm, it was therefore necessary to develop an Extreme UV lithography (EUV) process.
Understand that the different layers are etched on the silicon wafers with particularly short wavelengths. The design of the transistor doors is also adapted to avoid the quantum effects that take over at this scale (we are talking about elements that are only a few atoms wide). However, to deliver ever greater performance gains, TSMC, ASML and other founders like Samsung are also interested in increasing the number of component layers on each die..
These layers simultaneously allow the creation of more complex components – which is essential at these scales. While complicating the design of the chip. So for now, TSMC currently uses a 5nm process which allows up to 14 layers to be etched on the same component. The switch to 3 nm alone should deliver a 15% increase in power and 30% reduction in energy consumption at an equal level of complexity and number of transistors.
But it is undoubtedly possible to do even better: ASML is developing a technology which will burn up to 20 layers on the same die in 3 nm. Progress that should benefit both SoCs for smartphones and DRAM memory chips. With 3 nm, TSMC will opt for a design of so-called FinFET transistors: they are in fact transitors with two gates. The name FinFET comes from the shape of certain regions of the component which form kinds of lamellae on the surface of the die. This increases the frequency, while increasing the density of the components.
For the transition to 2 nm TSMC will further change the design of the transistors to switch to GAAFET technology (Gate All Around) developed by Samsung in parallel with MBCFET technology to go beyond 3 nm. Exciting innovations should thus be seen in the coming years as we approach the fundamental limits of silicon etching. Perhaps while waiting to find alternatives.