Intel, AMD e Arm joining forces? This unlikely scene has just become reality: the three companies, along with so many others, came together to develop the Universal Chiplet Interconnect Express (UCIe), open standard for creating chiplets. But what the heck is this and why is this concept so important?
Maybe you’ve used chiplets and don’t even know it. The concept is present in AMD Ryzen processors, for example. The trend is for the idea to be widely adopted by the semiconductor industry in the coming years, so much so that the need for standardization soon became evident.
What is chiplet?
We often think of a processor as a monolithic component, that is, one that has a defined structure within a single package. This thinking is not incorrect, but it can be limited by current standards, which admit that a processor is formed by more than one module, so to speak, within the same chip.
Well, a chiplet is the name given to each of these modules. You can have chiplets for the CPU cores and others for the GPU cores, for example. It’s as if several smaller chips — the chiplets — were put together to force a larger chip.
This approach has numerous advantages. One is waste reduction. In a monolithic design, small defects during manufacturing can cause the chip to be discarded; on a chip with chiplets, only the defective module would have to be discarded, not the entire unit.
Another advantage, perhaps the most relevant, is the greater ease of combining different technologies on a single chip. Proof of this is the proposal that Intel is developing to allow customers who need custom-made chips to combine, in a single unit, x86 cores with Arm and/or RISC-V cores.
Why was the UCIe created?
It is useless for the chip to be formed by two or more chiplets and these do not have an efficient communication with each other. The UCIe was conceived precisely for the industry to create and adopt an interconnection standard between these components.
This is important because chiplets from different manufacturers can be combined on a single chip. Standardization greatly reduces the risk of communication problems between them and makes it easier to define optimization parameters.
It is not by chance that, in addition to Intel, AMD and Arm, the consortium has the participation of companies such as Qualcomm, Samsung, TSMC and Ase Group.
Google, Microsoft and Meta (Facebook) are also present. Do not be surprised: the three companies do not operate directly in the semiconductor market, but develop their own chips for application in datacenters or artificial intelligence systems, for example.
About UCIe 1.0
In the official announcement, the consortium presented the UCIe 1.0 specifications. The definitions of this version cover, above all, the physical layer of communication, that is, the electrical signaling parameters that the chiplets must follow in order to “talk” to each other.
Just to give an example, these specifications encompass standards for two types of packaging: the simplest determines that the chiplets communicate through 16 data paths and up to 25 mm of space between them; the most advanced is based on 64 lanes and 2 mm spacing.
At the protocol layer, UCIe 1.0 works with the PCI Express and Compute Express Link standards, but manufacturers that have access to more advanced technologies — such as AMD with Infinity Fabric — will be able to use them and still remain compliant. with the specification.
As the version numbering suggests, this is just the beginning. The UCIe will continue to be developed to, among other attributes, open up 3D chips (with “stacked” components) more.